Adjustment of write timing in a memory device
US8730758B2 · kind B2 · utility
11Cited by
4References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 24, 2009 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Feb 18, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.