Patent · US Active

Method and system for calculating timing delay in a repeater network in an electronic circuit

US8731858B2 · kind B2 · utility

0Cited by

2References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Markus Buehler · Holzgerlingen, DE
Juergen Kuehl · Holzgerlingen, DE
Markus Olbrich · Langenhagen, DE
Philipp Panitz · Eppelheim, DE

Key dates

Filing date	Oct 13, 2009
Grant date	May 20, 2014
Priority date	—
Expiry date	Mar 20, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Calculating a timing delay in a repeater network in an electronic circuit. The repeater network comprises a plurality of driving cells. At least one loop comprising one or more pins and one or more driving cells for driving the loop is implemented. Each driving cell in the loop is arranged between two branches of the loop. For each driving cell, the loop is opened a plurality of times per driving cell, with one open at a time. A dedicated arrival time of a signal at each sink of the repeater network for the one open at a time per driving cell is calculated. The dedicated arrival time is stored. The calculation step and the storing step is repeated until the dedicated arrival time at each sink of the repeater network is available for each of the opens per driving cell.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.