Deadlock avoidance during store-mark acquisition
US8732407B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2008 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Feb 2, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments of the present invention provide a system that avoids deadlock while attempting to acquire store-marks on cache lines. During operation, the system keeps track of store-mark requests that arise during execution of a thread, wherein a store-mark on a cache line indicates that one or more associated store buffer entries are waiting to be committed to the cache line. In this system, store-mark requests are processed in a pipelined manner, which allows a store-mark request to be initiated before preceding store-mark requests for the same thread complete. Next, if a store-mark request fails, within a bounded amount of time, the system removes or prevents store-marks associated with younger store-mark requests for the same thread, thereby avoiding a potential deadlock that can arise when one or more other threads attempt to store-mark the same cache lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.