Variable resistance memory device and method of fabricating the same
US8735860B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2013 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Jan 16, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/884
Abstract
A variable resistance memory device includes a selection transistor, which includes a first doped region and a second doped region, a vertical electrode coupled to the first doped region of the selection transistor, a bit line coupled to the second doped region of the selection transistor, a plurality of word lines stacked on the substrate along a sidewall of the vertical electrode, variable resistance patterns between the word lines and the vertical electrode, and an insulating isolation layer between the word lines. The variable resistance patterns are spaced apart from each other in a direction normal to a top surface of the substrate by the insulating isolation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.