CMOS gate stack structures and processes
US8735987B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2012 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Jun 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
Abstract
A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.