Device for reducing contact resistance of a metal
US8736056B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2012 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Aug 31, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure for an integrated circuit with reduced contact resistance is disclosed. The structure includes a substrate, a cap layer deposited on the substrate, a dielectric layer deposited on the cap layer, and a trench embedded in the dielectric layer. The trench includes an atomic layer deposition (ALD) TaN or a chemical vapor deposition (CVD) TaN deposited on a side wall of the trench, a physical vapor deposition (PVD) Ta or a combination of the PVD Ta and a PVD TaN deposited on the ALD TaN or CVD TaN, and a Cu deposited on the PVD Ta or the combination of the PVD Ta and the PVD TaN deposited on the ALD TaN or the CVD TaN. The structure further includes a via integrated into the trench at bottom of the filled trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.