Aggregating data latches for program level determination
US8737125B2 · kind B2 · utility
5Cited by
18References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 7, 2012 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Nov 17, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—may be determined from the aggregated results of a single read step. A circuit for aggregating binary results of a read step includes parallel transistors with control gates connected to the data latches holding the binary results, so that current flow through the combined transistors depends on the binary results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.