3D integrated circuit device fabrication with precisely controllable substrate removal
US8738167B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2012 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Feb 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a non-transitory computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.