Systems and methods for increasing debugging visibility of prototyping systems
US8739089B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 28, 2012 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Aug 28, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations in field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.