Integration of shallow trench isolation and through-substrate vias into integrated circuit designs
US8742535B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2010 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Dec 16, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing an IC, comprising providing a substrate having a first side and a second opposite side, forming a STI opening in the first side of the substrate and forming a partial TSV opening in the first side of the substrate and extending the partial TSV opening. The extended partial TSV opening is deeper into the substrate than the STI opening. The method also comprises filling the STI opening with a first solid material and filling the extended partial TSV opening with a second solid material. Neither the STI opening, the partial TSV opening, nor the extended partial TSV opening penetrate an outer surface of the second side of the substrate. At least either: the STI opening and the partial TSV opening are formed simultaneously, or, the STI opening and the extended partial TSV opening are filled simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.