Wafer-level molded structure for package assembly
US8743561B2 · kind B2 · utility
7Cited by
27References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2010 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Jun 10, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure includes a bottom die; a top die bonded to the bottom die with the top die having a size smaller than the bottom die; and a molding compound over the bottom die and the top die. The molding compound contacts edges of the top die. The edges of the bottom die are vertically aligned to respective edges of the molding compound.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.