Integration scheme for dual work function metal gates
US8748246B2 · kind B2 · utility
1Cited by
2References
27Claims
0Family size
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Key dates
| Filing date | Dec 10, 2010 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Mar 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor includes a semiconductor substrate includes having a gate hardmask over the gate electrode layer during the formation of transistor source/drain regions. An independent work function adjustment process implants Group IIIa series dopants into a gate polysilicon layer of a PMOS transistor and implants lanthanide series dopants into a gate polysilicon layer of a NMOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.