Noble gas implantation region in top silicon layer of semiconductor-on-insulator substrate
US8748285B2 · kind B2 · utility
4Cited by
13References
12Claims
0Family size
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Key dates
| Filing date | Nov 28, 2011 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Jan 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A semiconductor structure includes a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a handle wafer, a buried oxide (BOX) layer on top of the handle wafer, and a top silicon layer on top of the BOX layer; and an implantation region located in the top silicon layer, the implantation region comprising a noble gas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.