Three dimensional non-volatile memory device and method of manufacturing the same
US8748966B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2011 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Nov 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/689
Abstract
A three dimensional non-volatile memory structure includes a plurality of interlayer dielectric layers and a plurality of control gates alternately stacked over a substrate, a channel formed to penetrate the plurality of interlayer dielectric layers and the plurality of control gates, a tunnel insulating layer formed to surround the channel, a plurality of floating gates disposed between the plurality of interlayer dielectric layers and the tunnel insulating layer, wherein the plurality of floating gates each have a thickness greater than a corresponding one of the interlayer dielectric layers, and a charge blocking layer disposed between the plurality of control gates and the plurality of floating gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.