Robust inspection alignment of semiconductor inspection tools using design information
US8750597B2 · kind B2 · utility
60Cited by
14References
16Claims
0Family size
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Key dates
| Filing date | Nov 23, 2011 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Aug 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of performing inspection alignment point selection for semiconductor devices includes importing, with a computer device, one or more semiconductor design files corresponding to an area of a semiconductor die; aligning a design taken from the one or more semiconductor design files with an image taken from a die of a semiconductor wafer; and selecting an alignment point and recording a portion of the design file corresponding to the alignment point as a master reference image.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.