Vertical stacking of field effect transistor structures for logic gates
US8754417B2 · kind B2 · utility
10Cited by
14References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 10, 2012 |
| Grant date | Jun 17, 2014 |
| Priority date | — |
| Expiry date | Sep 10, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Vertically stacked Field Effect Transistors (FETs) are created where a first FET and a second FET are controllable independently. The vertically stacked FETs may be connected in series or in parallel, thereby suitable for use as a portion of a NAND circuit or a NOR circuit. Epitaxial growth over a source and drain of a first FET, and having similar doping to the source and drain of the first FET provide a source and drain of a second FET. An additional epitaxial growth of a type opposite the doping of the source and drain of the first FET provides a body for the second FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.