High speed test circuit and method
US8754656B2 · kind B2 · utility
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4References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2012 |
| Grant date | Jun 17, 2014 |
| Priority date | — |
| Expiry date | Feb 8, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50012
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A high speed test circuit receives a tester clock from a tester and it conducts a test on a circuit under test. The high speed test circuit generates a high frequency clock according to the tester clock, so it is capable of operating in two frequencies. The high speed test circuit tests the circuit under test according to the high frequency clock, and it performs a low speed operation according to a low frequency clock, which is for example the tester clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.