Locked-loop quiescence apparatus, systems, and methods
US8754683B2 · kind B2 · utility
1Cited by
6References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2008 |
| Grant date | Jun 17, 2014 |
| Priority date | — |
| Expiry date | Mar 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/095
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatus, systems, and methods disclosed herein may initialize a delay-locked loop (DLL) or phase-locked loop (PLL) to achieve a locked condition and may then initiate a quiescent mode of operation. Quiescent operation may be achieved by breaking a feedback loop associated with the DLL or PLL to prevent updates to a variable delay line associated with the DLL and/or to a variable frequency oscillator associated with the PLL. An output clock phase associated with the DLL or PLL may thus be held substantially constant following a DLL initialization period. Additional embodiments are disclosed and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.