Etch stop layer formation in metal gate process
US8759172B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2012 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Apr 18, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/665
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.