System and method for micro-tiering in non-volatile memory
US8760922B2 · kind B2 · utility
12Cited by
3References
18Claims
0Family size
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Key dates
| Filing date | Apr 10, 2012 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Apr 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0685
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a storage device such as a solid state disk (SSD), a central controller communicates with a plurality of multi-chip memory packages. Each multi-chip memory package comprises a plurality of memory dies and a local processor, wherein the plurality of memory dies includes different memory tiers. The central controller may handle management of the virtual address space while the local processor in each MCP manages the storage of data within memory tiers in the memory dies of its respective MCP.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.