Writing bit alterable memories
US8760938B2 · kind B2 · utility
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28Claims
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Key dates
| Filing date | Oct 3, 2007 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Nov 9, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bit alterable memory may include current generators in a periphery outside the main memory core. Current may be generated in the periphery and driven into the core. As a result, the capacitance of the memory cells has a lowered effect. The current may be generated using the chip supply voltage and then mirrored using a pump voltage. In some embodiments, the mirroring may be ratioed at the partition level and multiplied at the plane level. A delay may be provided before applying the currents to the cell to accommodate for transients.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.