Banded computation architectures
US8762918B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2013 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Jun 3, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A convolution of the kernel over a layout in a multi-core processor system includes identifying a sector, called a dynamic band, of the layout including a plurality of evaluation points. Layout data specifying the sector of the layout is loaded in shared memory, which is shared by a plurality of processor cores. A convolution operation of the kernel and the evaluation points in the sector is executed. The convolution operation includes iteratively loading parts of the basis data set, called a stride, into space available in shared memory given the size of the layout data specifying the sector. A plurality of threads is executed concurrently using the layout data for the sector and the currently loaded part of the basis data set. The iteration for the loading basis data set proceeds through the entire data set until the convolution operation is completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.