System and method for efficient modeling of NPskew effects on static timing tests
US8768679B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2010 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | May 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method that simulates NPskew effects on a combination NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor) semiconductor device using slew perturbations includes performing a timing test by a computing device, by: (1) evaluating perturb slews in Strong N/Weak P directions on the combination semiconductor device for a timing test result; (2) evaluation perturb slews in Weak N/Strong P directions on the combination semiconductor device for a timing test result; and (3) evaluating unperturbed slews in a balanced condition on the combination semiconductor device for a timing test result. After each test is performed, a determination is made as to which evaluation of the perturbed and unperturbed slews produces a most conservative timing test result for the combination semiconductor device. An NPskew effect adjusted timing test result is finally output based on determining the most conservative timing test result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.