Patent · US Active

Automatic generation of wire tag lists for a metal stack

US8769468B1 · kind B1 · utility

4Cited by
11References
23Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 9, 2013
Grant dateJul 1, 2014
Priority date
Expiry dateJan 9, 2033

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F30/394
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.