Technique for forming a dielectric interlayer above a structure including closely spaced lines

US8772178B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Hartmut Ruelke · Dresden, DE
• Christof Streck · Coswig, DE
• Kai Frohberg · Meißen, DE

Key dates

• Filing date: Mar 16, 2005
• Grant date: Jul 8, 2014
• Expiry date: Sep 16, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

By depositing the lower portion of a silicon dioxide interlayer dielectric by means of SACVD or HDP-CVD techniques, the generation of voids may be reliably avoided even for devices having spaces between closely spaced lines on the order of 200 nm or less. Moreover, the bulk silicon dioxide material is deposited by well-established plasma enhanced CVD techniques, thereby providing the potential for using well-established process recipes for the subsequent CMP process, so that production yield and cost of ownership may be maintained at a low level.