Method and apparatus for scrubbing accumulated disturb data errors in an array of SMT MRAM memory cells including rewriting reference bits
US8775865B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 28, 2011 |
| Grant date | Jul 8, 2014 |
| Priority date | — |
| Expiry date | Jul 8, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/106
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data scrubbing apparatus corrects disturb errors occurring in a memory cell array, such as SMT MRAM cells. The data scrubbing apparatus activates scrubbing of the data and associated error correction bits based on a number of errors corrected, at a power up of the memory cell array, or a programmed time interval. The data scrubbing apparatus may generate an address describing the location of the memory cells to be scrubbed. The data scrubbing apparatus then commands the array of memory cells to write back the corrected data, the associated error correction bits, and reference bits. The data scrubbing apparatus provides a busy indicator externally during a write back of corrected data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.