Semiconductor package and methods of formation thereof
US8778733B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2012 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Apr 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method of forming a semiconductor package includes placing a first die and a second die over a carrier. At least one of the first and the second dies are covered with an encapsulation material to form an encapsulant having a top surface and an opposite bottom surface. The encapsulant is thinned from the bottom surface to expose a first surface of the first die without exposing the second die. The exposed first surface of the first die is selectively etched to expose a second surface of the first die. A back side conductive layer is formed so as to contact the first surface. The second die is separated from the back side conductive layer by a first portion of the encapsulant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.