Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US8779601B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2011 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Nov 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/157
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An eWLB package for 3D and PoP applications includes a redistribution layer on a support wafer. A semiconductor die is coupled to the redistribution layer, and solder balls are also positioned on the redistribution layer. The die and solder balls are encapsulated in a molding compound layer, which is planarized to expose top portions of the solder balls. A second redistribution layer is formed on the planarized surface of the molding compound layer. A ball grid array can be positioned on the second redistribution layer to couple the semiconductor package to a circuit board, or additional semiconductor dies can be added, each in a respective molding compound layer. The support wafer can act as an interposer, in which case it is processed to form TSVs in electrical contact with the first redistribution layer, and a redistribution layer is formed on the opposite side of the support substrate, as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.