Microprocessor cache line evict array
US8782348B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2008 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Jun 10, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1056
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for ensuring data coherency within a cache memory hierarchy of a microprocessor during an eviction of a cache line from a lower-level memory to a higher-level memory in the hierarchy includes an eviction engine and an array of storage elements. The eviction engine is configured to move the cache line from the lower-level memory to the higher-level memory. The array of storage elements are coupled to the eviction engine. Each storage element is configured to store an indication for a corresponding cache line stored in the lower-level memory. The indication indicates whether or not the eviction engine is currently moving the cache line from the lower-level memory to the higher-level memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.