Vector instruction execution to load vector data in registers of plural vector units using offset addressing logic
US8782376B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2011 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Apr 21, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3889
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor including: a first and at least a second data processing channel with enable logic for selectively enabling the second channel; logic for generating first and second storage addresses having a variable offset therebetween based on the same one or more address operands of the same storage access instruction; and circuitry for transferring data between the first address and a register of the first data processing channel and between the second address and a corresponding register of the second channel based on a same one or more register specifier operands of the access instruction. The first data processing channel performs an operation using one or more registers of the first data processing channel, and on condition of being enabled the second channel performs the same operation using a corresponding one or more of its own registers based on the same one or more operands of the data processing instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.