Advanced converters for memory cell sensing and methods
US8782474B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2013 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Aug 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/54
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A counter configuration operates in cooperation with a delay configuration such that the counter configuration counts an input interval based on a given clock speed and a given clock interval while the delay configuration provides an enhanced data output that is greater than what would otherwise be provided by the given clock speed. The counter configuration counts responsive to a selected edge in the clock interval. An apparatus in the form of a correction arrangement and an associated method are configured to monitor at least the delay configuration output for detecting a particular time relationship between an endpoint of the input interval and a nearest occurrence of the selected clock edge in the given clock signal that is indicative of at least a potential error in the enhanced data output and determining if the potential error is an actual error for subsequent use in correcting the enhanced data output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.