Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysis
US8782582B1 · kind B1 · utility
3Cited by
16References
22Claims
0Family size
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Key dates
| Filing date | Jul 30, 2013 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Jul 30, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention provides a method for detecting physical implementation hot-spots in a pre-placement integrated circuit design. The method first identifies physical issues at an object level. Physical issues include timing, routing congestion, clocking, scan, power, and thermal. The method then analyzes these physical issues over a collection of connected logic cell and large cell instances and determines a physical implementation hot-spot severity based on the number and severity of physical issues as well as the number of objects in the related collection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.