Physically aware logic synthesis of integrated circuit designs

US8782591B1 · kind B1 · utility

Assignee

• Cadence Design Systems, Inc. · US

Inventors

• Tsuwei Ku · Cupertino, US
• David John Seibert · Mountain View, US
• Huey-Yih Wang · Cupertino, US
• Hua Song · Fremont, US
• Kai Zhu · Yixing, CN
• Yu-Fang Chung · Cupertino, US
• Ankush Sood · San Jose, US

Key dates

• Filing date: Dec 31, 2012
• Grant date: Jul 15, 2014
• Expiry date: Dec 31, 2032

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2119/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In one embodiment of the invention, a method of synthesizing physical gates from register transfer logic code for an integrated circuit design is disclosed. The method includes reading a register transfer level (RTL) input file describing an integrated circuit design; parsing and translating the RTL input file into a plurality of Boolean logic equations; translating the plurality of Boolean logic equations into a plurality of logic primitives; placing the plurality of logic primitives into a floorplan of the integrated circuit design, wherein the placement of the plurality of logic primitives defines wire interconnects; and optimizing each of the plurality of Boolean logic equations in response to wire costs and wire timing delays.