Patent · US Active

Method for manufacturing a plurality of chips

US8785234B2 · kind B2 · utility

0Cited by

1References

24Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Gunther Mackh · Dresden, DE
Adolf Koller · Regensburg, DE

Key dates

Filing date	Oct 31, 2012
Grant date	Jul 22, 2014
Priority date	—
Expiry date	Oct 31, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method for manufacturing a plurality of chips comprises the step of providing a wafer comprising a plurality of chip areas separated by one or more dicing lines, wherein the chip areas are arranged on a first main surface, the step of providing a laser absorption layer on a second main surface opposite to the first main surface and the step of providing a backside metal stack on the laser absorption layer. After that a laser light is applied to the laser absorption layer along the dicing lines before the chips are singulated along the dicing lines by using stealth dicing.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.