Inventor · Dresden, DE

Gunther Mackh

26Patents
3h-index
45Co-inventors
63Inventor score

Filing activity: Oct 2, 2002 → Oct 18, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US9040389B2 Singulation processes Electricity 5 Active
US8951915B2 Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements Electricity 3 Active
US7660175B2 Integrated circuit, method for acquiring data and measurement system Physics 3 Active
US8697574B2 Through substrate features in semiconductor substrates Electricity 2 Active
US6884688B2 Method for producing a MOS transistor and MOS transistor Electricity 2 Expired
US9570352B2 Method of dicing a wafer and semiconductor chip Electricity 2 Active
US9147624B2 Chip comprising a backside metal stack Electricity 2 Active
US8436707B2 System and method for integrated inductor Emerging Cross-Sectional Technologies 1 Active
US7202527B2 MOS transistor and ESD protective device each having a settable voltage ratio of the lateral breakdown voltage to the vertical breakdown voltage Electricity 1 Expired
US9159620B2 Semiconductor structure and method for making same Electricity 1 Active
US8822329B2 Method for making conductive interconnects Electricity 1 Active
US12424495B2 Chip separation supported by back side trench and adhesive therein Electricity 0 Active
US9040354B2 Chip comprising a fill structure Electricity 0 Active
US9911655B2 Method of dicing a wafer and semiconductor chip Electricity 0 Active
US8704338B2 Chip comprising a fill structure Electricity 0 Active
US10008318B2 System and method for integrated inductor Emerging Cross-Sectional Technologies 0 Active
US12406940B2 Semiconductor chip having a crack stop structure Electricity 0 Active
US7816791B2 Bonding pad for contacting a device Electricity 0 Active
US12374632B2 Semiconductor device and method for manufacturing a plurality of semiconductive devices Performing Operations; Transporting 0 Active
US10748801B2 Carrier arrangement and method for processing a carrier by generating a crack structure Electricity 0 Active
US8785234B2 Method for manufacturing a plurality of chips Electricity 0 Active
US8809165B2 Method for fusing a laser fuse and method for processing a wafer Electricity 0 Active
US9196670B2 Through substrate features in semiconductor substrates Electricity 0 Active
US9576875B2 Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements Electricity 0 Active
US10090214B2 Wafer and method for processing a wafer Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.