Method of forming a memory cell by reducing diffusion of dopants under a gate
US8785307B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2012 |
| Grant date | Jul 22, 2014 |
| Priority date | — |
| Expiry date | Dec 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6892
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a memory cell includes forming a conductive floating gate over the substrate, forming a conductive control gate over the floating gate, forming a conductive erase gate laterally to one side of the floating gate and forming a conductive select gate laterally to an opposite side of the one side of the floating gate. After the forming of the floating and select gates, the method includes implanting a dopant into a portion of a channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate that is less than ninety degrees and greater than zero degrees.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.