Static random access memory test structure
US8787074B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2011 |
| Grant date | Jul 22, 2014 |
| Priority date | — |
| Expiry date | Sep 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory (SRAM) test structure includes a p-type source/drain implant region comprising contacts (CAs), wherein the CAs in the p-type source/drain implant region comprise a first plurality of bit line, ground, and node CAs, and wherein the CAs in the p-type source/drain implant region are grounded during an inspection of the SRAM test structure; and an ungrounded region, the ungrounded region being distinct from the p-type source/drain implant region and being ungrounded during the inspection of the SRAM test structure, the ungrounded region comprising contacts (CAs) and rectangular contacts (CArecs) comprising a second plurality of bit line, ground, and node CAs, and further comprising a first plurality of Vdd CAs and rectangular contacts (CArecs), and wherein a CA or CArec in the ungrounded region is grounded during the inspection in the event of a short to a CA in the p-type source/drain implant region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.