Method and apparatus for reducing read disturb in memory
US8787078B2 · kind B2 · utility
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2References
20Claims
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Key dates
| Filing date | Dec 13, 2013 |
| Grant date | Jul 22, 2014 |
| Priority date | — |
| Expiry date | Dec 13, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.