N-well switching circuit
US8787096B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2013 |
| Grant date | Jul 22, 2014 |
| Priority date | — |
| Expiry date | Feb 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.