Methods of forming CMOS transistors using tensile stress layers and hydrogen plasma treatment
US8790972B2 · kind B2 · utility
2Cited by
2References
17Claims
0Family size
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Key dates
| Filing date | Aug 19, 2010 |
| Grant date | Jul 29, 2014 |
| Priority date | — |
| Expiry date | Aug 19, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/405
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming integrated circuit devices include forming a PMOS transistor having a SiGe channel region therein and then exposing at least a portion of the PMOS transistor to a hydrogen plasma. A tensile stress layer may be formed on the PMOS transistor. The exposing step may include exposing source and drain regions of the PMOS transistor to the hydrogen plasma.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.