Via non-standard limiting parameters
US8793627B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Jul 29, 2014 |
| Priority date | — |
| Expiry date | Mar 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methodology enabling designs with a reduced V0 distance to M1 inner vertex restriction is disclosed. Embodiments include determining a limiting parameter α for manufacture of an SAV proximate to an M1 inner vertex; defining a coordinate system in terms of horizontal and vertical distances x and y, respectively, between the SAV and the M1 inner vertex angle; calculating α as a function of x and y; simulating the calculation of α as a function of x and y; calculating a baseline angle α1 as a function of x and y; simulating calculation of the baseline angle α1 as a function of x and y; extracting a 3σ value of the baseline angle α1 from the simulation; and designing a semiconductor cell with an SAV proximate to an M1 inner vertex, the cell having a limiting parameter α minimum value equal to the 3σ value of the baseline angle α1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.