Inventor · Cohoes, NY, US

Jason E. Stephens

40Patents
10h-index
66Co-inventors
70Inventor score

Filing activity: Jan 16, 2012 → Nov 15, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US9818641B1 Apparatus and method of forming self-aligned cuts in mandrel and a non-mandrel lines of an array of metal lines Electricity 20 Active
US9825031B1 Methods of forming a high-k contact liner to improve effective via separation distance and the resulting devices Electricity 16 Active
US9852986B1 Method of patterning pillars to form variable continuity cuts in interconnection lines of an integrated circuit Electricity 14 Active
US9818640B1 Apparatus and method of forming self-aligned cuts in a non-mandrel line of an array of metal lines Electricity 14 Active
US9818651B2 Methods, apparatus and system for a passthrough-based architecture Electricity 14 Active
US8969199B1 Methods of forming a circuit that includes a cross-coupling gate contact structure wherein the circuit is to be manufactured using a triple patterning process Electricity 13 Active
US9236437B2 Method for creating self-aligned transistor contacts Electricity 11 Active
US9202751B2 Transistor contacts self-aligned in two dimensions Electricity 11 Active
US8839168B2 Self-aligned double patterning via enclosure design Physics 10 Active
US9224617B2 Forming cross-coupled line segments Electricity 10 Active
US8793627B1 Via non-standard limiting parameters Physics 9 Active
US9006100B2 Middle-of-the-line constructs using diffusion contact structures Electricity 8 Active
US9786545B1 Method of forming ANA regions in an integrated circuit Electricity 8 Active
US8946914B2 Contact power rail Electricity 6 Active
US9818623B2 Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit Electricity 5 Active
US8856715B1 Capacitor designs for integrated circuits utilizing self-aligned double patterning (SADP) Physics 5 Active
US8987816B2 Contact power rail Electricity 5 Active
US9691626B1 Method of forming a pattern for interconnection lines in an integrated circuit wherein the pattern includes gamma and beta block mask portions Electricity 5 Active
US9779943B2 Compensating for lithographic limitations in fabricating semiconductor interconnect structures Electricity 4 Active
US11043418B2 Middle of the line self-aligned direct pattern contacts Electricity 3 Active
US8598633B2 Semiconductor device having contact layer providing electrical connections Electricity 3 Active
US10236350B2 Method, apparatus and system for a high density middle of line flow Electricity 3 Active
US9412655B1 Forming merged lines in a metallization layer by replacing sacrificial lines with conductive lines Electricity 2 Active
US9472455B2 Methods of cross-coupling line segments on a wafer Electricity 2 Active
US10181420B2 Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias Electricity 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.