Inducing channel strain via encapsulated silicide formation
US8796099B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2012 |
| Grant date | Aug 5, 2014 |
| Priority date | — |
| Expiry date | Dec 5, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/794
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming semiconductor structures having channel regions strained by encapsulated silicide formation. Embodiments include forming a transistor, depositing an interlevel dielectric (ILD) layer above the transistor, forming contact recesses exposing portions of source/drain regions of the transistor, forming metal-rich silicide layers on the exposed portions of the source/drain regions, forming metal contacts in the contact recesses above the metal-rich silicide layers, and converting the metal-rich silicide layer to a silicon-rich silicide layer. In other embodiments, the metal-rich silicide layers are formed on the source/drain regions prior to ILD layer deposition. Embodiments further include forming a transistor, depositing an ILD layer above the transistor, forming contact recesses exposing portions of source/drain regions of the transistor, forming metal liners in the contact recesses, forming metal fills in the contact recesses, and forming silicide layers on the source/drain regions by reacting portions of the metal liners with portions of the source/drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.