Embedded wafer level ball grid array bar systems and methods
US8796139B2 · kind B2 · utility
2Cited by
0References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2012 |
| Grant date | Aug 5, 2014 |
| Priority date | — |
| Expiry date | Dec 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bar formed from a reconstituted wafer and containing one or more conductive material filled voids is used to electrically and physically connect the top and bottom packages in a package-on-package (PoP) package. The bar is disposed in the fan out area of the lower package forming the PoP package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.