MRAM with sidewall protection and method of fabrication

US8796795B2 · kind B2 · utility

Assignee

• Avalanche Technology, Inc. · US

Inventors

• Kimihiro Satoh · Wilsonville, US
• Yiming Huai · Pleasanton, US
• Jing Zhang · Los Altos, US
• Ebrahim Abedifard · Sunnyvale, US

Key dates

• Filing date: Aug 1, 2011
• Grant date: Aug 5, 2014
• Expiry date: Nov 20, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/826

Abstract

BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.