Shielded gate field effect transistors
US8803207B2 · kind B2 · utility
20Cited by
42References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2011 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Jun 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one general aspect, an apparatus can include a trench disposed in a semiconductor region, a shield dielectric layer lining a lower portion of a sidewall of the trench and a bottom surface of the trench, and a gate dielectric lining a upper portion of the sidewall of the trench. The apparatus can also include a shield electrode disposed in a lower portion of the trench and insulated from the semiconductor region by the shield dielectric layer, and an inter-electrode dielectric (IED) disposed in the trench over the shield electrode where the shield electrode has a curved top surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.