Vertical mirror in a silicon photonic circuit
US8803268B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2013 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Apr 26, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02B6/4214
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A vertical total internal reflection (TIR) mirror and fabrication thereof is made by creating a re-entrant profile using crystallographic silicon etching. Starting with an SOI wafer, a deep silicon etch is used to expose the buried oxide layer, which is then wet-etched (in HF), opening the bottom surface of the Si device layer. This bottom silicon surface is then exposed so that in a crystallographic etch, the resulting shape is a re-entrant trapezoid with facets These facets can be used in conjunction with planar silicon waveguides to reflect the light upwards based on the TIR principle. Alternately, light can be coupled into the silicon waveguides from above the wafer for such purposes as wafer level testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.