Patent · US Active

Semiconductor device including a stress relief layer and method of manufacturing

US8803297B2 · kind B2 · utility

6Cited by

1References

16Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Peter Nelle · Munich, DE
Uwe Schmalzbauer · Neubiberg, DE
Juergen Holzmueller · Reichenbach/Oberlausitz, DE
Markus Zundel · Egmating, DE

Key dates

Filing date	Aug 10, 2012
Grant date	Aug 12, 2014
Priority date	—
Expiry date	Aug 10, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor device includes a main body having a single crystalline semiconductor body. A layered structure directly adjoins a central portion of a main surface of the main body and includes a hard dielectric layer provided from a first dielectric material with Young's modulus greater than 10 GPa. A stress relief layer directly adjoins the layered structure opposite to the main body and extends beyond an outer edge of the layered structure. Providing the layered structure at a distance to the edge of the main body and covering the outer surface of the layered structures with the stress relief layer enhances device reliability.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.