Stacked integrated circuit package system
US8803299B2 · kind B2 · utility
2Cited by
17References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2006 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Dec 9, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked integrated circuit package system is provided forming a lead and a die paddle from a lead frame, forming a first integrated circuit die having an interconnect provided thereon, placing a second integrated circuit die over the first integrated circuit die and the die paddle, connecting the second integrated circuit die and the lead, and encapsulating the first integrated circuit die and the second integrated circuit die with a portion of the lead and the interconnect exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.