Delamination resistance of stacked dies in die saw
US8803332B2 · kind B2 · utility
26Cited by
70References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2010 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Aug 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure includes a first die including TSVs; a second die over and bonded to the first die, with the first die having a surface facing the second die; and a molding compound including a portion over the first die and the second die. The molding compound contacts the surface of the second die. Further, the molding compound includes a portion extending below the surface of the second die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.